| Author |
Message |
QQ
Guest
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 Posted:
Fri Dec 09, 2005 8:35 am Post subject:
SMPS switching loss question |
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Hi,
In a buck regulator with a rectifier diode if:
a. I use a driver of size 'X' to drive the control nmos (top nmos) of
area 'Y'
b. I use a driver of size 'X/2' to drive a control nmos (top nmos) of
area 'Y/5'
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnon?
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnoff?
I thought that the answer to both these questions should be yes, but in
simulaton I find that during turn on the 'overlap' time during turnon
is actually higher in case b as compared to case a. Is this expected in
a real world situation? Why is this so ?
Thanks
QQ
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Fred Bartoli
Guest
|
| Posted:
Fri Dec 09, 2005 9:35 am Post subject:
Re: SMPS switching loss question |
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"QQ" <q_q_404@hotmail.com> a écrit dans le message de
news:1134095708.864237.147560@g47g2000cwa.googlegroups.com...
| Quote: | Hi,
In a buck regulator with a rectifier diode if:
a. I use a driver of size 'X' to drive the control nmos (top nmos) of
area 'Y'
b. I use a driver of size 'X/2' to drive a control nmos (top nmos) of
area 'Y/5'
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnon?
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnoff?
I thought that the answer to both these questions should be yes, but in
simulaton I find that during turn on the 'overlap' time during turnon
is actually higher in case b as compared to case a. Is this expected in
a real world situation? Why is this so ?
|
In a real homework situation, are you expected to cheat and have your work
done by others?
Look a bit harder and light will come.
--
Thanks,
Fred. |
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QQ
Guest
|
| Posted:
Fri Dec 09, 2005 9:35 am Post subject:
Re: SMPS switching loss question |
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This isnt "homework". Just trying to get some understanding and didnt
know anyone else to ask.
Thanks
QQ
Fred Bartoli wrote:
| Quote: | "QQ" <q_q_404@hotmail.com> a écrit dans le message de
news:1134095708.864237.147560@g47g2000cwa.googlegroups.com...
Hi,
In a buck regulator with a rectifier diode if:
a. I use a driver of size 'X' to drive the control nmos (top nmos) of
area 'Y'
b. I use a driver of size 'X/2' to drive a control nmos (top nmos) of
area 'Y/5'
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnon?
Will the switching losses (due to Vds Id overlap) be less in case 'b'
during turnoff?
I thought that the answer to both these questions should be yes, but in
simulaton I find that during turn on the 'overlap' time during turnon
is actually higher in case b as compared to case a. Is this expected in
a real world situation? Why is this so ?
In a real homework situation, are you expected to cheat and have your work
done by others?
Look a bit harder and light will come.
--
Thanks,
Fred. |
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| Back to top |
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