| Author |
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John O'Flaherty
Guest
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 Posted:
Wed Mar 09, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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Geir Klemetsen wrote:
| Quote: | "John O'Flaherty" <quiasmox@yahoo.com> skrev i melding
news:39601tF5ujsraU1@individual.net...
Geir Klemetsen wrote:
"BR" <slackin@nonsense.comcast.net> skrev i melding
news:Xns9612685AA1E27hatespam@216.196.97.136...
Hello,
Is there a circuit that can delay a pulse train without affecting its
width? The pulse width is about 1.5ms to 2ms, every 20ms (RC servo
signals). The delay needed is less than that, perhaps up to 1 ms. It
would be convenient if it were variable.
The only thing I can think of right now, is to couple several
TTL-inverters
in series. Each one of them works as a delay line. The only thing you
need
to know is the delay of each one of them. A typical IC would be an 7404.
At about 10ns each, it would take 100,000 of them to get 1 ms delay;
still, with six per package it would only be 16,667 ics.
Ok, forget that. What about using a delay line, such as those used in older
televisions instead?
Now the only thing i cannot help with is the pinouts for such one thing and
the delay it provides...
|
I think those things were in the microsecond range, and weren't really
for clean digital signals. You'd probably have to use some active
circuit like a one-shot to get to the millisecond area.
--
john
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Guest
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| Posted:
Thu Mar 10, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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On Semiconductor still shows dual 64 bit shift registers. Stack up 512
bits, clock at 500KHz and get 1mS delay with 2 uSec resolution. Or, did
someone say PIC?
GG |
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Guest
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| Posted:
Fri Mar 11, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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Not what I had in mind, no. The OP wants a delay on both the leading
and trailing edge, I.E. maintain the original pulse width, just delay
it. Think of this as a 1 bit digitizer and the shift register is the
memory. If your clock is good, no temperature variations, very
predictable and pretty simple. Take the output from different bit
counts and/or vary the clock rate for different/multiple delays.
GG
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Kitchen Man
Guest
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| Posted:
Fri Mar 11, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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On 9 Mar 2005 21:02:25 -0800 in sci.electronics.basics,
stratus46@yahoo.com wrote msg
<1110430945.494805.255750@o13g2000cwo.googlegroups.com>:
| Quote: | On Semiconductor still shows dual 64 bit shift registers. Stack up 512
bits, clock at 500KHz and get 1mS delay with 2 uSec resolution. Or, did
someone say PIC?
|
I don't think there's a system clock involved. The delay has to be
triggered by the event that is to be delayed. Have I got that right?
--
Al Brennan |
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Kitchen Man
Guest
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| Posted:
Fri Mar 11, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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On Tue, 08 Mar 2005 23:29:46 -0600 in sci.electronics.basics, John
O'Flaherty <quiasmox@yahoo.com> wrote msg
<397fubF5ubqv3U1@individual.net>:
| Quote: | Ok, forget that. What about using a delay line, such as those used in older
televisions instead?
Now the only thing i cannot help with is the pinouts for such one thing and
the delay it provides...
I think those things were in the microsecond range, and weren't really
for clean digital signals. You'd probably have to use some active
circuit like a one-shot to get to the millisecond area.
|
I remember using crystal delay lines, and you're right, they were in the
microsecond range and were used on RADAR synchronizers. I've seen them
in ATE, as well.
There are sophisticated trigger delay devices available, but such things
are costly. Depending on the OP's budget on building this
servomechanism, I would highly recommend using one. You feed the
trigger signal in, and can tap off one or more programmable delays. If
you get one with one output for each servo (or if your sync signal is
one of the servos), you can digitally program each one separately. The
digital alignments and separate synchronization should make a well
behaved machine.
--
Al Brennan |
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Kitchen Man
Guest
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| Posted:
Mon Mar 14, 2005 1:01 am Post subject:
Re: Delay without affecting pulse width |
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On 10 Mar 2005 21:32:34 -0800 in sci.electronics.basics,
stratus46@yahoo.com wrote msg
<1110519153.984390.183960@g14g2000cwa.googlegroups.com>:
| Quote: | Not what I had in mind, no. The OP wants a delay on both the leading
and trailing edge, I.E. maintain the original pulse width, just delay
it. Think of this as a 1 bit digitizer and the shift register is the
memory. If your clock is good, no temperature variations, very
predictable and pretty simple. Take the output from different bit
counts and/or vary the clock rate for different/multiple delays.
|
I guess I didn't explain myself clearly. I don't think there is a
system clock, so to use this approach, a system clock has to be
developed and synchronized to the release pulse.
--
Al Brennan |
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Guest
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| Posted:
Mon Mar 14, 2005 1:15 am Post subject:
Re: Delay without affecting pulse width |
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The clock doesn't need to be synchronized with anything. Free running
would be fine. The 'downside' is a 2 uSec window with a 500 KHz clock.
Use a bigger FIFO and faster clock for a smaller window. I got the
impression from earlier posts that the exact timing wasn't critical.
Think of it more like a crude 1 bit recorder/player.
GG |
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John Fields
Guest
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| Posted:
Mon Mar 14, 2005 5:28 am Post subject:
Re: Delay without affecting pulse width |
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On Mon, 07 Mar 2005 19:44:21 -0600, BR <slackin@nonsense.comcast.net>
wrote:
| Quote: | John Fields <jfields@austininstruments.com> wrote in
news:kbdp211k5pm4367ap70l7jjcaah5ivinjk@4ax.com:
On Mon, 07 Mar 2005 12:15:30 -0600, BR
slackin@nonsense.comcast.net> wrote:
Hello,
Is there a circuit that can delay a pulse train without
affecting its width? The pulse width is about 1.5ms to 2ms,
every 20ms (RC servo signals). The delay needed is less than
that, perhaps up to 1 ms. It would be convenient if it were
variable.
---
Can you provide a timing diagram to show what you mean or
verbally explain what you mean by "delay"?
The best I can do is give a description of the apparatus. It
involves three RC servos mounted on a rotating ring used to form a
gripper system. Each gripper pad is located equidistant about the
outside rim of a small 5" dia. hemispherical bowl containing water.
The opening of the 5" bowl must be in full view. The 5" bowl is
floating in a larger bowl filled with water. All three servos are
connected to one signal output of an EZ servo 1 chip (a pre-
programed controller). A problem occurs when the bowl is released.
The gripper releases the bowl as fast as it can when the signal
pulse width changes abruptly from 1725µs to 1650µs. However, the
differences between servos always causes the bowl to drift slowly
away from the lagging servo. This is determined by releasing the
bowl while the ring is stationary. Adjusting the servo mounting hw
only reduces the problem. So, I'm looking for a way to fine tune
the release and minimize linear motion of the bowl. If this can't
be done with delay lines I would appreciate any suggestions.
|
---
The easiest way, I think, would be to use something like an HC123 or a
4538. Use the first section to generate the delay and to trigger the
second section after that delay. The output of the second section
will be the pulse you want and, if you use this approach, will also be
adjustable.
See "Delay without affecting pulse width" on
alt.binaries.schematics.electronic for a schematic and circuit
description.
--
John Fields |
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Jamie
Guest
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| Posted:
Mon Mar 14, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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Kitchen Man wrote:
| Quote: | On 10 Mar 2005 21:32:34 -0800 in sci.electronics.basics,
stratus46@yahoo.com wrote msg
1110519153.984390.183960@g14g2000cwa.googlegroups.com>:
Not what I had in mind, no. The OP wants a delay on both the leading
and trailing edge, I.E. maintain the original pulse width, just delay
it. Think of this as a 1 bit digitizer and the shift register is the
memory. If your clock is good, no temperature variations, very
predictable and pretty simple. Take the output from different bit
counts and/or vary the clock rate for different/multiple delays.
I guess I didn't explain myself clearly. I don't think there is a
system clock, so to use this approach, a system clock has to be
developed and synchronized to the release pulse.
i think what your looking for is a continous running clock that |
inputs it's pulses to an AND gate. when the other input is on, the
pulse will appear on the output of the AND gate in sync because there
is no initial starting of an OSC/timer
etc.
is that what your looking for ? |
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John Fields
Guest
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| Posted:
Mon Mar 14, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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On Tue, 08 Mar 2005 09:13:35 +0000, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:
| Quote: | John Fields <jfields@austininstruments.com> wrote:
On Mon, 07 Mar 2005 12:15:30 -0600, BR <slackin@nonsense.comcast.net
wrote:
Hello,
Is there a circuit that can delay a pulse train without affecting its
width? The pulse width is about 1.5ms to 2ms, every 20ms (RC servo
signals). The delay needed is less than that, perhaps up to 1 ms. It
would be convenient if it were variable.
---
Can you provide a timing diagram to show what you mean or verbally
explain what you mean by "delay"?
I assumed he meant this:
http://www.terrypin.dial.pipex.com/Images/PulseTrainDelay.gif
|
---
Yes, I think you're right; thanks. I posted a solution to abse a
little while ago under the same subject as this thread, albeit with an
error... U1-8 is ground, not U1A-Q. :-(
--
John Fields |
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BR
Guest
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| Posted:
Mon Mar 14, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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John Fields <jfields@austininstruments.com> wrote in
news:b0j931d9ehq67l4rtkb7uf21ubaijbn11l@4ax.com:
| Quote: | The easiest way, I think, would be to use something like an
HC123 or a 4538. Use the first section to generate the delay and
to trigger the second section after that delay. The output of
the second section will be the pulse you want and, if you use
this approach, will also be adjustable.
See "Delay without affecting pulse width" on
alt.binaries.schematics.electronic for a schematic and circuit
description.
|
I have some 4528 Thanks for the schematic.
Ben
-- |
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Guest
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| Posted:
Tue Mar 15, 2005 6:10 am Post subject:
Re: Delay without affecting pulse width |
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Nope, even simpler than that. No gate required because no
synchronization is required. But you're right that the clock would need
to run continuously. The pulse to be delayed is applied to the input of
the shift register. I assume the logic families are compatible I.E.
you're not trying to connect ECL into TTL without the proper interface.
The delayed pulse(s) extracted some number of shift cycles later from
one or more 'taps'. This is nothing more than a digital equivalent of
the old analog CCD audio chips from the '70s.
GG |
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