| Author |
Message |
Guest
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 Posted:
Wed Dec 07, 2005 5:35 pm Post subject:
Re: pci and caching |
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Andy Peters wrote:
| Quote: | As the board booted, the monitor enumerated the PCI bus and assigned
valid base addresses to all of the PCI devices. From its command line,
you could do the equivalent of PEEK and POKE to the PLX peripheral
control registers or to the board's custom registers. Standard
memory-dump and memory-modify commands were available, too,
So, what John wants to do -- peek and poke registers, etc -- is
reasonable.
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This was kind of a tangent to the caching discussion. But sure, no
issue with doing this. What you are doing is essentially is putting
the knowledge of the hardware/registers into the peek/poke operator
instead of a device driver.
In order to get at the high addresses that the BIOS will put the PCI
device at, I suspect that some sort of extended memory add-on
will be required (haven't worked in DOS in ages). Whether it
defaults to caching the memory or not will be dependent on that
software. If I were writing it and had to pick just one, I'd disable
caching for that memory range to ensure compatibility, though at
the cost of performance.
| Quote: | As for caching -- that really depends on how the system controller chip
is set up. I don't know to what extent the BIOS firmware sets up a
PC's system controller; presumably, it does enough to find the boot
device for a higher-level OS, to which it passes control. The OS then
may set up the system controller in ways that depend on its needs. One
presumes that the system controller driver honors the cacheable bit and
doesn't cache a memory space declared as non-cacheable!
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Reasonable, although it depends on the OS. In the ones I've
worked with, you can't take a default but have to indicate the
characteristics (including cache/non-cache) that you need.
Also, assuming an OS/drivers that left the setup entirely to
the BIOS, the implication would be that the entire PCI range
would be non-cached since the BIOS has no way to know if
caching will cause grief for any particular card.
Steve
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TC
Guest
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| Posted:
Thu Dec 08, 2005 9:35 am Post subject:
Re: pci and caching |
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"Mark McDougall" <markm@vl.com.au> wrote in message
news:4393bb75$0$23327$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
| Quote: | Keith wrote:
That doesn't change the cacheability. Caches are a processor thing
and *NOT* under control of any PCI device.
Which begs the question, why would the PCI spec refer to something that
has nothing to do with PCI?
If a PCI memory space is marked as 'pre-fetchable' then it guarantees,
among other things, that the act of pre-fetching memory has no
side-effects. This means nothing more than the fact that it may be a
suitable candidate for caching, if the platform supports it. In this case,
a master may issue MRL (& MRM) commands.
OTOH, cache-coherency (which I assume you're hinting at) is a different
problem altogether - especially if you've got multiple bus masters
accessing PCI memory space with their own caches. However, this is a
*system* problem and (IMHO) not really any concern of the PCI bus spec
group to mandate that PCI memory is not 'cacheable' - whatever that means
in each context!
In fact, there's little discussion what-so-ever in the spec (that I can
see) about 'caches' - which is just what I would expect.
BTW I'm quite happy to be shown the error in my reasoning!
Regards,
Mark
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PCI devices (peripherals) identify via Base Address Registers (BARs) the
size and type(s) of address space (IO, memory or prefecthable memory) that
they need the BIOS and/or operating system (plug and play code) to be mapped
as physical addresses on the bus. These addresses are typically accesed by
device drivers (but might also be accessed by other devices). The statement
that...
"If a PCI memory space is marked as 'pre-fetchable' then it guarantees,
among other things, that the act of pre-fetching memory has no
side-effects."
.... is the best summary statement of the signifigance of 'pre-fetchable'
memory on PCI. It is used purely as a performance optimization that allows
for use of burst read transactions (specifically MRL and MRM) when accessing
that address region.
This has nothing to do with cacheing. While the original PCI specification
envisioned the ability to have cacheable memory accessed via the PCI bus
(and includes SBO# and SDONE to implement a cache coherency protocol for
PCI) I am unaware of any system or design that ever implemented this. In
subsequent specifications (i.e. PCI 2.2) it was made clear that this
functionality was being demoted and marked for removal in future
specification revisions.
Hope this helps.
TC |
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John Larkin
Guest
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| Posted:
Thu Dec 08, 2005 11:44 pm Post subject:
Re: pci and caching |
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On Thu, 08 Dec 2005 04:02:16 GMT, "TC" <noone@nowhere.com> wrote:
| Quote: |
"Mark McDougall" <markm@vl.com.au> wrote in message
news:4393bb75$0$23327$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
Keith wrote:
That doesn't change the cacheability. Caches are a processor thing
and *NOT* under control of any PCI device.
Which begs the question, why would the PCI spec refer to something that
has nothing to do with PCI?
If a PCI memory space is marked as 'pre-fetchable' then it guarantees,
among other things, that the act of pre-fetching memory has no
side-effects. This means nothing more than the fact that it may be a
suitable candidate for caching, if the platform supports it. In this case,
a master may issue MRL (& MRM) commands.
OTOH, cache-coherency (which I assume you're hinting at) is a different
problem altogether - especially if you've got multiple bus masters
accessing PCI memory space with their own caches. However, this is a
*system* problem and (IMHO) not really any concern of the PCI bus spec
group to mandate that PCI memory is not 'cacheable' - whatever that means
in each context!
In fact, there's little discussion what-so-ever in the spec (that I can
see) about 'caches' - which is just what I would expect.
BTW I'm quite happy to be shown the error in my reasoning!
Regards,
Mark
PCI devices (peripherals) identify via Base Address Registers (BARs) the
size and type(s) of address space (IO, memory or prefecthable memory) that
they need the BIOS and/or operating system (plug and play code) to be mapped
as physical addresses on the bus. These addresses are typically accesed by
device drivers (but might also be accessed by other devices). The statement
that...
"If a PCI memory space is marked as 'pre-fetchable' then it guarantees,
among other things, that the act of pre-fetching memory has no
side-effects."
... is the best summary statement of the signifigance of 'pre-fetchable'
memory on PCI. It is used purely as a performance optimization that allows
for use of burst read transactions (specifically MRL and MRM) when accessing
that address region.
This has nothing to do with cacheing. While the original PCI specification
envisioned the ability to have cacheable memory accessed via the PCI bus
(and includes SBO# and SDONE to implement a cache coherency protocol for
PCI) I am unaware of any system or design that ever implemented this. In
subsequent specifications (i.e. PCI 2.2) it was made clear that this
functionality was being demoted and marked for removal in future
specification revisions.
Hope this helps.
TC
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Thanks. The concensus seems to be that the Bios allocates requested
PCIbus memory resources but they are never cached. That seems to align
with my experience.
John
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The Real Andy
Guest
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| Posted:
Fri Dec 09, 2005 4:28 pm Post subject:
Re: pci and caching |
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On Sun, 04 Dec 2005 11:35:00 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
<snip>
| Quote: | tragedies of our time. Think of how things would be if IBM had gone
with the 68K and anybody but Bill.
|
Well, we would al be using apple macs and bill gates would be poor.
There would be no dos, and no doubt all the linux guys would then hate
the origonal Mac OS. Then again, we could be really unluck and be all
stuck using OS2 blah blah blah. |
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Guest
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| Posted:
Fri Dec 09, 2005 5:35 pm Post subject:
Re: pci and caching |
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"Mark McDougall" <markm@vl.com.au> wrote in message
| Quote: | This has nothing to do with cacheing. While the original PCI specification
envisioned the ability to have cacheable memory accessed via the PCI bus
(and includes SBO# and SDONE to implement a cache coherency protocol for
PCI) I am unaware of any system or design that ever implemented this. In
subsequent specifications (i.e. PCI 2.2) it was made clear that this
functionality was being demoted and marked for removal in future
specification revisions.
|
Note that these signals are related to cache within PCI bridges and
targets that support cache. They aren't involved when the cache is
within the CPU. So you still rely on software setting up the range
of memory on the PCI device as non-cached (ie, non-CPU-cached)
even as the above mechanism is deprecated.
I hadn't thought about caching within the bridges before you
mentioned it in this thread. Ouch, I can see why it's deprecated.
There's generally good OS support for a device driver to disable
the cache within the CPU for the range of memory corresponding
to the card, but wouldn't be able to touch this in the bridge chip
very easily. Posted writes to memory mapped hardware registers
are bad enough, but cached would be a killer in cases like our
cards.
Steve |
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