| Author |
Message |
Arie de Muynck
Guest
|
 Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
"John Larkin" ...
| Quote: | The small errors we're seeing may be due to cmos switch leakage, but
the error TCs are looking linear enough that leakage is probably not a
big issue... it should be sorta exponential on temperature, and we're
not seeing that.
Switch resistance doesn't matter here as long as it's constant for the
duration of the two measurements. We're taking about 130 millisec for
each measurement, 260 total. It might be that the current (about 6 mA
when we're measuring a 100 ohm RTD) is heating the cmos switch enough
to give it a r-versus-t curve that matters. 6 mA, 75 ohms typ, gives
around 3 milliwatts in the switch. The HCT switch is about 75 ohms and
increases about 0.25 ohms/K. So, what's the thermal coefficient of one
fet in an HCT4051? 1000 k/w maybe?
If it increases 3K as a result of the switched current, we'll have
0.75 ohms increase, serious by our standards. But what's the thermal
tau?
|
Have you considered the thermal gradient in the chip may cause offset
voltages from the thermocouple like junctions (also Al-Si bonding points
etc) in the chip? I've seen 10..100 uV offsets when a 4051 chip (turned ON)
was next to a dissipating element. What's the equivalent offset voltage you
see?
Arie de Muynck
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Joerg
Guest
|
| Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
Hello Bill,
| Quote: |
The manufacturer's specified leakage current specification used to be
set by the limitiations of their measuring gear and the time available
to take the measurement.
|
If you look at the HCT405x specs you'll see that they specified very
different leakage values for the 4051 versus the 4052 and 4053. They've
got to have a reason for that.
| Quote: | I don't know how leaky modern CMOS has become.
|
My impression is that CMOS processes for the logic families are a whole
lot better in variations than they were 20 years ago. And I have heard
quite some horror stories about the situation 30 years ago.
Regards, Joerg
http://www.analogconsultants.com |
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John Larkin
Guest
|
| Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
On Thu, 01 Dec 2005 16:25:22 -0500, Phil Hobbs
<pcdh@SpamMeSenseless.pergamos.net> wrote:
| Quote: | John Larkin wrote:
On Thu, 1 Dec 2005 21:26:27 +0100, "Arie de Muynck"
send.spam.to@spammer.org> wrote:
"John Larkin" ...
Assuming a couple K of self-heating in the 4051, and a few uV/K
thermoelectric effect, we could have very roughly 10-50 (?) microvolts
of error injected into the middle of the series resistor pair, in the
ballpark of the error we're seeing. The error should go as i^2, which
we can analyze to see if this is an actual candidate effect to explain
(some of) the residual errors.
John,
TC coefficient for silicon to any metal is about _700_uv/K_. Ugly ugly
ugly.
|
Ghastly. Look at the graph at the end!
http://www.uni-konstanz.de/physik/Jaeckle/papers/thermopower/node1.html
Are p-n couples used as thermal imagers?
| Quote: | From your schematic, it looks as though TC offsets of sections B and C
are not cancelled by the 4-wire ratiometric approach.
|
Yeah, but there's no current in those switches. There are three
separate 4051's, separate packages.
John
|
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Phil Hobbs
Guest
|
| Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
John Larkin wrote:
| Quote: | On Thu, 1 Dec 2005 21:26:27 +0100, "Arie de Muynck"
send.spam.to@spammer.org> wrote:
"John Larkin" ...
Assuming a couple K of self-heating in the 4051, and a few uV/K
thermoelectric effect, we could have very roughly 10-50 (?) microvolts
of error injected into the middle of the series resistor pair, in the
ballpark of the error we're seeing. The error should go as i^2, which
we can analyze to see if this is an actual candidate effect to explain
(some of) the residual errors.
|
John,
TC coefficient for silicon to any metal is about _700_uv/K_. Ugly ugly
ugly.
From your schematic, it looks as though TC offsets of sections B and C
are not cancelled by the 4-wire ratiometric approach.
Cheers,
Phil Hobbs |
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|
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Joerg
Guest
|
| Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
Hello John,
| Quote: | The small errors we're seeing may be due to cmos switch leakage, but
the error TCs are looking linear enough that leakage is probably not a
big issue... it should be sorta exponential on temperature, and we're
not seeing that.
|
I don't know what the leakage mechanism is, that would be Jim's domain.
However, unless I misunderstood something then 0.4uA out of 6mA is
already 66ppm. So a few ten ppm seems like you are getting a good deal
from those '51 chips. If they spec them at 0.4uA max versus 0.1uA for
the other muxes then it's unlikely you'd be getting 0.1uA from a '51.
| Quote: | Switch resistance doesn't matter here as long as it's constant for the
duration of the two measurements. We're taking about 130 millisec for
each measurement, 260 total. It might be that the current (about 6 mA
when we're measuring a 100 ohm RTD) is heating the cmos switch enough
to give it a r-versus-t curve that matters. 6 mA, 75 ohms typ, gives
around 3 milliwatts in the switch. The HCT switch is about 75 ohms and
increases about 0.25 ohms/K. So, what's the thermal coefficient of one
fet in an HCT4051? 1000 k/w maybe?
If it increases 3K as a result of the switched current, we'll have
0.75 ohms increase, serious by our standards. But what's the thermal
tau?
|
Maybe one way to find out is to scoot the measurement window back and
forth a few tens of milliseconds.
Whenever I wanted to know those kind of things from app engineers I was
often told that such data is not available and that I should use this
newer xyz gizmo chip. Which, of course, was an order of magnitude more
expensive.
Regards, Joerg
http://www.analogconsultants.com |
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|
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John Larkin
Guest
|
| Posted:
Fri Dec 02, 2005 1:35 am Post subject:
Re: HCT4051 leakage |
|
|
On Thu, 1 Dec 2005 21:26:27 +0100, "Arie de Muynck"
<send.spam.to@spammer.org> wrote:
| Quote: | "John Larkin" ...
The small errors we're seeing may be due to cmos switch leakage, but
the error TCs are looking linear enough that leakage is probably not a
big issue... it should be sorta exponential on temperature, and we're
not seeing that.
Switch resistance doesn't matter here as long as it's constant for the
duration of the two measurements. We're taking about 130 millisec for
each measurement, 260 total. It might be that the current (about 6 mA
when we're measuring a 100 ohm RTD) is heating the cmos switch enough
to give it a r-versus-t curve that matters. 6 mA, 75 ohms typ, gives
around 3 milliwatts in the switch. The HCT switch is about 75 ohms and
increases about 0.25 ohms/K. So, what's the thermal coefficient of one
fet in an HCT4051? 1000 k/w maybe?
If it increases 3K as a result of the switched current, we'll have
0.75 ohms increase, serious by our standards. But what's the thermal
tau?
Have you considered the thermal gradient in the chip may cause offset
voltages from the thermocouple like junctions (also Al-Si bonding points
etc) in the chip? I've seen 10..100 uV offsets when a 4051 chip (turned ON)
was next to a dissipating element. What's the equivalent offset voltage you
see?
Arie de Muynck
|
Yikes, that is a real possibility. I did note in this ng, recently,
about thermocouple gradients in opto-ssr's!
Assuming a couple K of self-heating in the 4051, and a few uV/K
thermoelectric effect, we could have very roughly 10-50 (?) microvolts
of error injected into the middle of the series resistor pair, in the
ballpark of the error we're seeing. The error should go as i^2, which
we can analyze to see if this is an actual candidate effect to explain
(some of) the residual errors.
But wait...
vref-------+------------
|
r1 adc
|
+------------
|
|
|
4051a
|
|
+------4051b------
|
r2 adc
|
+------4051c------
|
|
gnd
We're doing a 4-wire voltage-drop measurement on each of the two
resistors. So adding a potential internal to the analog switch 4051a
in effect only changes the overall reference voltage. And the ohms
calculation is ratiometric, so the actual voltage doesn't matter. So
what's left is a time-domain *change* in this error component during
the measurement process.
This precision stuff is interesting. Very low-order effects become
important, and they are the devil to find and quantify.
John |
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John Larkin
Guest
|
| Posted:
Sat Dec 10, 2005 9:12 am Post subject:
Re: HCT4051 leakage |
|
|
On Thu, 1 Dec 2005 09:01:04 +0100, "Fred Bartoli"
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
| Quote: |
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> a écrit dans le
message de news:d47so1h0tsdv3lr2jub84772s11n32aa9i@4ax.com...
Hi,
Has anybody measured typical leakage currents for an HCT4051 analog
mux? I'm wondering about both ESD diode leakage (ie, to rails) and
leakage through open switches. I'm running 0 and +5V rails.
Indications are that everybody's 0.1 uA max spec is wildly
pessimistic, but I was wondering if anybody knows more, before I have
to drag my butt into the lab and make actual measurements. It's a lot
easier to sit here and type and eat bon-bons.
We're scanning eight RTDs. A +2.5 volt reference goes through a
precision 270 ohm resistor and gets mux'd to a selected RTD. The
voltage drop across the RTD gets differentially mux'd, too. A 24-bit
delta-sigma ADC digitizes the voltage drop across the 270, then the
voltage across the RTD, and does the math. We're getting errors in the
tens of PPM, tolerable, but we're curious where they're coming from.
The sensitivity analysis math here is a nuisance.
I did measure an old CD4053 about two years ago (sorry did not have 74HC).
It had +/-5V supplies and was arranged for 0V common mode at both switch
ends.
IIRC the leakages were about 1pA at room temperature.
One thing that surpised me was that, while static leakages were that low,
dynamic leakages (100kHz switching) were not negligeable at all.
Quizz: how do you pump fraction of a uA through the resistors with the
switch wired as below?
4053
.------------.
| | ___
| |--|___|- GND
___ | o---/| 50K
GND -|___|--|---o--__ |
50K | o--- | ___
| \|--|___|- GND
'------------' 50K
|
Clock it?
I don't think I have a charge injection problem. After I configure the
switches to put the two resistors in series, I wait 4 milliseconds
before I digitize Rx (which takes 125 millisec) and then digitize
Rref, another 125. Since the worst node has an impedance near 100
ohms, and the capacitances are small, the RC tau is way under 1 usec.
My calculator won't do e^-4000 but I'm guessing it's pretty small.
Hmmm... connecting the resistors does apply a load, about 6 mA, to my
2.5 volt reference. The same ref drives the ADC, so it's all
ratiometric, *unless* the ref has a transient bounce from the 6 mA
load step. Now I must need one of those super-low-noise multi-fet amps
to analyze my voltage reference bounce!
John |
|
| Back to top |
|
|
Chris Jones
Guest
|
| Posted:
Sat Dec 10, 2005 5:28 pm Post subject:
Re: HCT4051 leakage |
|
|
John Larkin wrote:
| Quote: | On Thu, 1 Dec 2005 09:01:04 +0100, "Fred Bartoli"
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> a écrit dans le
message de news:d47so1h0tsdv3lr2jub84772s11n32aa9i@4ax.com...
Hi,
Has anybody measured typical leakage currents for an HCT4051 analog
mux? I'm wondering about both ESD diode leakage (ie, to rails) and
leakage through open switches. I'm running 0 and +5V rails.
Indications are that everybody's 0.1 uA max spec is wildly
pessimistic, but I was wondering if anybody knows more, before I have
to drag my butt into the lab and make actual measurements. It's a lot
easier to sit here and type and eat bon-bons.
We're scanning eight RTDs. A +2.5 volt reference goes through a
precision 270 ohm resistor and gets mux'd to a selected RTD. The
voltage drop across the RTD gets differentially mux'd, too. A 24-bit
delta-sigma ADC digitizes the voltage drop across the 270, then the
voltage across the RTD, and does the math. We're getting errors in the
tens of PPM, tolerable, but we're curious where they're coming from.
The sensitivity analysis math here is a nuisance.
I did measure an old CD4053 about two years ago (sorry did not have 74HC).
It had +/-5V supplies and was arranged for 0V common mode at both switch
ends.
IIRC the leakages were about 1pA at room temperature.
One thing that surpised me was that, while static leakages were that low,
dynamic leakages (100kHz switching) were not negligeable at all.
Quizz: how do you pump fraction of a uA through the resistors with the
switch wired as below?
4053
.------------.
| | ___
| |--|___|- GND
___ | o---/| 50K
GND -|___|--|---o--__ |
50K | o--- | ___
| \|--|___|- GND
'------------' 50K
Clock it?
I don't think I have a charge injection problem. After I configure the
switches to put the two resistors in series, I wait 4 milliseconds
before I digitize Rx (which takes 125 millisec) and then digitize
Rref, another 125. Since the worst node has an impedance near 100
ohms, and the capacitances are small, the RC tau is way under 1 usec.
My calculator won't do e^-4000 but I'm guessing it's pretty small.
Hmmm... connecting the resistors does apply a load, about 6 mA, to my
2.5 volt reference. The same ref drives the ADC, so it's all
ratiometric, *unless* the ref has a transient bounce from the 6 mA
load step. Now I must need one of those super-low-noise multi-fet amps
to analyze my voltage reference bounce!
John
|
If you do an experiment where you greatly slow down the cycling of the MUX,
is it still bad? I thought that Sigma-delta ADCs aren't generally supposed
to work well when muxed, their digital filters contain history about old
input signals.
Chris |
|
| Back to top |
|
|
John Larkin
Guest
|
| Posted:
Sat Dec 10, 2005 5:35 pm Post subject:
Re: HCT4051 leakage |
|
|
On Sat, 10 Dec 2005 11:28:21 +0000, Chris Jones
<lugnut808@nospam.yahoo.com> wrote:
| Quote: | John Larkin wrote:
On Thu, 1 Dec 2005 09:01:04 +0100, "Fred Bartoli"
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> a écrit dans le
message de news:d47so1h0tsdv3lr2jub84772s11n32aa9i@4ax.com...
Hi,
Has anybody measured typical leakage currents for an HCT4051 analog
mux? I'm wondering about both ESD diode leakage (ie, to rails) and
leakage through open switches. I'm running 0 and +5V rails.
Indications are that everybody's 0.1 uA max spec is wildly
pessimistic, but I was wondering if anybody knows more, before I have
to drag my butt into the lab and make actual measurements. It's a lot
easier to sit here and type and eat bon-bons.
We're scanning eight RTDs. A +2.5 volt reference goes through a
precision 270 ohm resistor and gets mux'd to a selected RTD. The
voltage drop across the RTD gets differentially mux'd, too. A 24-bit
delta-sigma ADC digitizes the voltage drop across the 270, then the
voltage across the RTD, and does the math. We're getting errors in the
tens of PPM, tolerable, but we're curious where they're coming from.
The sensitivity analysis math here is a nuisance.
I did measure an old CD4053 about two years ago (sorry did not have 74HC).
It had +/-5V supplies and was arranged for 0V common mode at both switch
ends.
IIRC the leakages were about 1pA at room temperature.
One thing that surpised me was that, while static leakages were that low,
dynamic leakages (100kHz switching) were not negligeable at all.
Quizz: how do you pump fraction of a uA through the resistors with the
switch wired as below?
4053
.------------.
| | ___
| |--|___|- GND
___ | o---/| 50K
GND -|___|--|---o--__ |
50K | o--- | ___
| \|--|___|- GND
'------------' 50K
Clock it?
I don't think I have a charge injection problem. After I configure the
switches to put the two resistors in series, I wait 4 milliseconds
before I digitize Rx (which takes 125 millisec) and then digitize
Rref, another 125. Since the worst node has an impedance near 100
ohms, and the capacitances are small, the RC tau is way under 1 usec.
My calculator won't do e^-4000 but I'm guessing it's pretty small.
Hmmm... connecting the resistors does apply a load, about 6 mA, to my
2.5 volt reference. The same ref drives the ADC, so it's all
ratiometric, *unless* the ref has a transient bounce from the 6 mA
load step. Now I must need one of those super-low-noise multi-fet amps
to analyze my voltage reference bounce!
John
If you do an experiment where you greatly slow down the cycling of the MUX,
is it still bad? I thought that Sigma-delta ADCs aren't generally supposed
to work well when muxed, their digital filters contain history about old
input signals.
Chris
|
(Hmmm, my last post got lost somewhere in usenet limbo for a week or
two)
This is an AD7793 24-bit delta-sigma. It has a mode where you can
trigger it to digitize. It takes twice as long to deliver data as in
the continuous mode, but has no memory of the previous input.
We're not seeing crosstalk between channels, just nonlinearity. We'll
get a few more boards nest week and, if they all have the same trend,
I'll just stick a polynomial into the firmware to uncurve the data and
never understand it.
John |
|
| Back to top |
|
|
Chris Jones
Guest
|
| Posted:
Sun Dec 11, 2005 12:18 am Post subject:
Re: HCT4051 leakage |
|
|
John Larkin wrote:
| Quote: | On Sat, 10 Dec 2005 11:28:21 +0000, Chris Jones
lugnut808@nospam.yahoo.com> wrote:
John Larkin wrote:
On Thu, 1 Dec 2005 09:01:04 +0100, "Fred Bartoli"
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> a écrit dans
le message de news:d47so1h0tsdv3lr2jub84772s11n32aa9i@4ax.com...
Hi,
Has anybody measured typical leakage currents for an HCT4051 analog
mux? I'm wondering about both ESD diode leakage (ie, to rails) and
leakage through open switches. I'm running 0 and +5V rails.
Indications are that everybody's 0.1 uA max spec is wildly
pessimistic, but I was wondering if anybody knows more, before I have
to drag my butt into the lab and make actual measurements. It's a lot
easier to sit here and type and eat bon-bons.
We're scanning eight RTDs. A +2.5 volt reference goes through a
precision 270 ohm resistor and gets mux'd to a selected RTD. The
voltage drop across the RTD gets differentially mux'd, too. A 24-bit
delta-sigma ADC digitizes the voltage drop across the 270, then the
voltage across the RTD, and does the math. We're getting errors in the
tens of PPM, tolerable, but we're curious where they're coming from.
The sensitivity analysis math here is a nuisance.
I did measure an old CD4053 about two years ago (sorry did not have
74HC). It had +/-5V supplies and was arranged for 0V common mode at both
switch ends.
IIRC the leakages were about 1pA at room temperature.
One thing that surpised me was that, while static leakages were that
low, dynamic leakages (100kHz switching) were not negligeable at all.
Quizz: how do you pump fraction of a uA through the resistors with the
switch wired as below?
4053
.------------.
| | ___
| |--|___|- GND
___ | o---/| 50K
GND -|___|--|---o--__ |
50K | o--- | ___
| \|--|___|- GND
'------------' 50K
Clock it?
I don't think I have a charge injection problem. After I configure the
switches to put the two resistors in series, I wait 4 milliseconds
before I digitize Rx (which takes 125 millisec) and then digitize
Rref, another 125. Since the worst node has an impedance near 100
ohms, and the capacitances are small, the RC tau is way under 1 usec.
My calculator won't do e^-4000 but I'm guessing it's pretty small.
Hmmm... connecting the resistors does apply a load, about 6 mA, to my
2.5 volt reference. The same ref drives the ADC, so it's all
ratiometric, *unless* the ref has a transient bounce from the 6 mA
load step. Now I must need one of those super-low-noise multi-fet amps
to analyze my voltage reference bounce!
John
If you do an experiment where you greatly slow down the cycling of the
MUX,
is it still bad? I thought that Sigma-delta ADCs aren't generally
supposed to work well when muxed, their digital filters contain history
about old input signals.
Chris
(Hmmm, my last post got lost somewhere in usenet limbo for a week or
two)
This is an AD7793 24-bit delta-sigma. It has a mode where you can
trigger it to digitize. It takes twice as long to deliver data as in
the continuous mode, but has no memory of the previous input.
We're not seeing crosstalk between channels, just nonlinearity. We'll
get a few more boards nest week and, if they all have the same trend,
I'll just stick a polynomial into the firmware to uncurve the data and
never understand it.
John
|
Fair enough it sounds like the fact that it is sigma-delta is nothing to do
with the problems you are seeing.
By the way, are you able to measure the voltage of the RTD and precision
resistor with no current flowing also? Perhaps there is a thermal EMF or
something like that. If it is leakage in the ESD diodes, then if the
voltages were similar leading to similar leakage with and without the
current flowing (hard to arrange?) then it might be possible to compensate
for the leakage that way.
Chris |
|
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