| Author |
Message |
sam
Guest
|
 Posted:
Fri Feb 11, 2005 11:12 pm Post subject:
Clock Divider in a 22V10 |
|
|
Hello all:
I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.
I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.
I have been thinking about how best to do this,
using what I have.
Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.
With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.
By the way I also have a bunch of 74ls112 dual
J/K flip flops lying around (about 25). I
thought I might use that along with the 22v10'
to realize my clock divider.
Any ideas?
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Ken Smith
Guest
|
| Posted:
Fri Feb 11, 2005 11:12 pm Post subject:
Re: Clock Divider in a 22V10 |
|
|
In article <pssp01940r9trdauq7epc8l4fsee71c8ti@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
[...]
| Quote: | Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."
|
I think John meant this but it isn't clear so:
If you make the decoded output from the fast section registered. you get
the combined logic without adding a lot of delay.
The whole thing is well withing the 22V10s reach.
--
--
kensmith@rahul.net forging knowledge |
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John Larkin
Guest
|
| Posted:
Sat Feb 12, 2005 12:06 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
On Fri, 11 Feb 2005 17:12:36 GMT, sam <sam@here.com> wrote:
| Quote: | Hello all:
I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.
I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.
I have been thinking about how best to do this,
using what I have.
Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.
With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.
|
Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."
John
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John Larkin
Guest
|
| Posted:
Sat Feb 12, 2005 2:40 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
On Fri, 11 Feb 2005 19:33:52 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:
| Quote: | In article <pssp01940r9trdauq7epc8l4fsee71c8ti@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
[...]
Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."
I think John meant this but it isn't clear so:
If you make the decoded output from the fast section registered. you get
the combined logic without adding a lot of delay.
|
Actually, no; it can just be a static decode of one fast counter state
that enables the slower counter. It's no different from any other
carry. If you have a pin to spare, the carry state can be explicitly
decoded and then used in the counter below; if not, you have to
include all the decode terms in every flop of the lower counter, which
is a nuisance.
| Quote: | The whole thing is well withing the 22V10s reach.
|
Right; it's only 6 MHz.
Counters *are* a pain in a 22V10; there's no XOR available, so as the
counters get longer the number of logic terms explodes. It's tedious
to do by hand.
John |
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tlbs
Guest
|
| Posted:
Sat Feb 12, 2005 2:55 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
Back in 1988, I had to make a large counter in a CPLD. I used Altera's
EP610, which is similar to the 22V10's. Altera's flops could be
switched between "D" and "T" type flops, so making a synchronous ripple
counter was a simple task. I don't know if the 22V10's have that
option to switch flops to "T"-type. If they don't you could always
configure them as "T"-type in the feedback terms and that would make
the counter logic easier, anyway. I don't see a problem running at 6
MHz to generate a 154 kHz clock -- that's only a 6-bit counter. |
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Ken Smith
Guest
|
| Posted:
Sat Feb 12, 2005 2:58 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
In article <0m5q01t63g4fmadvvtfu79aeu71plhfm1q@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
| Quote: | On Fri, 11 Feb 2005 19:33:52 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:
In article <pssp01940r9trdauq7epc8l4fsee71c8ti@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
[...]
Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."
I think John meant this but it isn't clear so:
If you make the decoded output from the fast section registered. you get
the combined logic without adding a lot of delay.
Actually, no; it can just be a static decode of one fast counter state
that enables the slower counter. It's no different from any other
carry. If you have a pin to spare, the carry state can be explicitly
decoded and then used in the counter below; if not, you have to
include all the decode terms in every flop of the lower counter, which
is a nuisance.
|
Yes, at low speeds this works, such as the 6MHz that is the case here.
At higher speeds, the second layer of logic can become a source of
troubles.
| Quote: | Counters *are* a pain in a 22V10; there's no XOR available, so as the
counters get longer the number of logic terms explodes. It's tedious
to do by hand.
|
Yes, thats why God made the copy and paste operations. Each equation
builds up from the previous. For longer counters a psudo-random
generator using a shift register and one XOR can often save you a lot of
terms. This can be the way to go if you are trying to divide by something
like 245.
--
--
kensmith@rahul.net forging knowledge |
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Jim Granville
Guest
|
| Posted:
Sat Feb 12, 2005 3:10 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
sam wrote:
| Quote: | Hello all:
I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.
I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.
I have been thinking about how best to do this,
using what I have.
Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.
With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.
By the way I also have a bunch of 74ls112 dual
J/K flip flops lying around (about 25). I
thought I might use that along with the 22v10'
to realize my clock divider.
|
No need to use any additional logic, the 22V10 can /40,
but you will need a square wave on the clock.
To do both MOD5 and MOD8,
you need Mod8.CountEnable = (Mod5 == 0)
so that Mod8 clocks at 6.MHz (common clock in the 22V10), but is only
ENABLED to change one in 5 clocks. - the rest of the time, it holds
value.
With a 22V10, you have the resource to separate the BAUD and system
clocks : use 6 bits for divide by 40, and the other 4 bits allows
programmable divide by 2..16, which you can set on IP pins, and so vary
the Sys clock. ( or, indeed the BAUD clock, should you want to try >
9600 bd )
To vary the BAUD clock, you would code the /5, and then
have a /2../8, for 9600..- then you can get 9600 - 38.4Kbd
If you want the 1MHz to be an average more precise value, you can
even code a MOD6/MOD7 counter, and select that on a 6:40 basis,
so mostly it divides by 6, but 15% of the time, it divides by 7.
You then have 1MHz with 0.0009765625 error
Good software for 22V10 code is Atmel's free WinCUPL.
-jg |
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Meindert Sprang
Guest
|
| Posted:
Sat Feb 12, 2005 3:51 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:0m5q01t63g4fmadvvtfu79aeu71plhfm1q@4ax.com...
| Quote: | Counters *are* a pain in a 22V10;
|
Nah, I used to use Tango PLD.
Below is an example of an up/down counter:
module(in HOLD, CLK; reg io D7..0; io UP; out WR)
{
/* setup some stuff */
group D[D7..0];
D[].oe = HI;
D[].ck = CLK;
D[].aclr = 0;
D[].pre = 0;
UP.oe = 1;
WR.oe = HI;
if (HOLD==0)
{
if (UP.fb) D[]++; /* D is counter, count up */
else D[]--; /* or count down, voila... */
WR = CLK;
}
else
{
D[] = D[];
WR = HI;
}
Meindert |
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John Larkin
Guest
|
| Posted:
Sat Feb 12, 2005 4:22 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
On Fri, 11 Feb 2005 22:51:37 +0100, "Meindert Sprang"
<mhsprang@NOcustomSPAMware.nl> wrote:
| Quote: | "John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:0m5q01t63g4fmadvvtfu79aeu71plhfm1q@4ax.com...
Counters *are* a pain in a 22V10;
Nah, I used to use Tango PLD.
Below is an example of an up/down counter:
module(in HOLD, CLK; reg io D7..0; io UP; out WR)
{
/* setup some stuff */
group D[D7..0];
D[].oe = HI;
D[].ck = CLK;
D[].aclr = 0;
D[].pre = 0;
UP.oe = 1;
WR.oe = HI;
if (HOLD==0)
{
if (UP.fb) D[]++; /* D is counter, count up */
else D[]--; /* or count down, voila... */
WR = CLK;
}
else
{
D[] = D[];
WR = HI;
}
Meindert
|
Yeah, that's a lot easier than APEEL, where you have to grind out the
product terms.
" NOW DO THE COUNTER BITS...
MA1 = /MA1 * /MAX
MA2 = /MA2 * MA1 * /MAX
+ MA2 * /MA1 * /MAX
MA3 = /MA3 * MA2 * MA1 * /MAX
+ MA3 * /MA2 * /MAX
+ MA3 * /MA1 * /MAX
MA4 = /MA4 * MA3 * MA2 * MA1 * /MAX
+ MA4 * /MA3 * /MAX
+ MA4 * /MA2 * /MAX
+ MA4 * /MA1 * /MAX
MA5 = /MA5 * MA4 * MA3 * MA2 * MA1 * /MAX
+ MA5 * /MA4 * /MAX
+ MA5 * /MA3 * /MAX
+ MA5 * /MA2 * /MAX
+ MA5 * /MA1 * /MAX
etc...
So in a 22V10 the product terms get burned up fast as the counter gets
longer, no matter how you compile it.
Luckily, we don't use simple PLDs much any more; now it's mostly
Xilinx FPGAs and the occasional Coolrunner for dinky stuff.
John |
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Bob Stephens
Guest
|
| Posted:
Sat Feb 12, 2005 4:36 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
On Fri, 11 Feb 2005 12:40:41 -0800, John Larkin wrote:
| Quote: | Counters *are* a pain in a 22V10; there's no XOR available, so as the
counters get longer the number of logic terms explodes. It's tedious
to do by hand.
John
|
I found an *OLD* one of mine compiled with AMD's 'PLPL' logic compiler -
which used to be free - and did give you an XOR operator - (%);
Made counters pretty easy.
Bob
DEVICE ad2b (p22v10)
" same as Redcor ad2.pld except master reset "
PIN
" Generates address bits 0 - 6 "
"---- Output Pin Assignments ----"
compare1 = 18 (output active_low combinatorial)
compare2 = 19 (output active_low combinatorial)
latch = 17 (output active_high combinatorial)
a[6] = 14 (output active_high registered)
a[5] = 15 (output active_high registered)
a[4] = 16 (output active_high registered)
a[3] = 20 (output active_high registered)
a[2] = 21 (output active_high registered)
a[1] = 22 (output active_high registered)
a[0] = 23 (output active_high registered)
busy2=1 (clk_input) "add_ctr_adv "
d[6] = 2 (input combinatorial)
d[5] = 3 (input combinatorial)
d[4] = 4 (input combinatorial)
d[3] = 5 (input combinatorial)
d[2] = 6 (input combinatorial)
d[1] = 7 (input combinatorial)
d[0] = 8 (input combinatorial)
master = 9 (input combinatorial)
busy = 11 (input combinatorial) ;
"Logic Equation Section"
BEGIN
enable(a[0:6]) = #b1111111;
enable(compare1,compare2,latch)= #b111;
reset(a[0:6]) = /master; "reset to 0"
a[0]=/a[0];
a[1]=a[1]%a[0];
a[2]=a[2]%(a[1]*a[0]);
a[3]=a[3]%(a[2]*a[1]*a[0]);
a[4]=a[4]%(a[3]*a[2]*a[1]*a[0]);
a[5]=a[5]%(a[4]*a[3]*a[2]*a[1]*a[0]);
a[6]=a[6]%(a[5]*a[4]*a[3]*a[2]*a[1]*a[0]);
compare1=(a[0]%d[0])*(a[1]%d[1])*(a[2]%d[2])*(a[3]%d[3]);
compare2=(a[4]%d[4])*(a[5]%d[5])*(a[6]%d[6]);
latch=/compare1*/compare2*/busy;
END. |
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Meindert Sprang
Guest
|
| Posted:
Sat Feb 12, 2005 4:47 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:1gbq015ibg617j0nrmnj227cllfkphlj5j@4ax.com...
| Quote: | Yeah, that's a lot easier than APEEL, where you have to grind out the
product terms.
" NOW DO THE COUNTER BITS...
MA1 = /MA1 * /MAX
MA2 = /MA2 * MA1 * /MAX
+ MA2 * /MA1 * /MAX
MA3 = /MA3 * MA2 * MA1 * /MAX
+ MA3 * /MA2 * /MAX
+ MA3 * /MA1 * /MAX
|
<snip>
Ha, and exactly that could be distilled from the output of TangoPLD
| Quote: |
So in a 22V10 the product terms get burned up fast as the counter gets
longer, no matter how you compile it.
|
Correct, however my example *was* made for a 22V10. And it worked (8 bits
wide).
Meindert |
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sam
Guest
|
| Posted:
Sat Feb 12, 2005 4:59 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
On Fri, 11 Feb 2005 10:06:21 -0800, John Larkin wrote:
| Quote: | Clock all the flops at the same rate (you have to, anyhow) and decode
a single state of the faster counter and use that as a clock enable on
the slower counter, effectively a "carry in."
|
Thanks John.
So basically I would setup 3 Dflop outputs to
count through
0 - 2 - 6 - 4 - 5 - 7 - 3 -1 glitch free
(I have been working with PAL's for only a few
months CANT you tell ;))
then use 7 (decoded) to do two things
1) toggle one JK flip flop in the 74ls112
this gets fed as my system clock
2) enable the second clock (use reserved pin
"Clk2Enable")
the second can count through
0 - 2 - 6 - 4 - 5
then use 5 (decoded) to
1) clear "Clk2Enable"
2) toggle second JK flip flop in the 74ls112
this gets fed to my 8251 UART's baud clk pin.
Is that what you mean?
Thanks to all for the help and suggestions.
I am trying to realize my dream ... designing
a game machine.
I thought I'd start by designing a 6504 sbc
from scratch ... I am almost done ... its just
at the last minute I thought to use the same
crystal ... and divide down to get the clock
I want for the processor and the uart
there goes the Keep It Simple S..... principle! |
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CBFalconer
Guest
|
| Posted:
Sat Feb 12, 2005 4:59 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
John Larkin wrote:
| Quote: |
.... snip ...
Counters *are* a pain in a 22V10; there's no XOR available, so as
the counters get longer the number of logic terms explodes. It's
tedious to do by hand.
|
Consider shift registers with a feedback function. For example,
shifting left with the feedback being the complement of the high
order bit, you get the sequence:
000
001
011
111
110
100
000 -> i.e. a scale of 6.
You can build anything you like with a suitable feedback. Take the
nor of the middle and left bits and:
000
001
011
110
100
000 -> i.e. a scale of 5.
Always check what the unused codes will do. For the scale of 5
010 -> 100 ok, main sequence
101 -> 010 ok, because of above
110 -> 100 ok, main sequence.
but for the scale of 6:
010 -> 101 -> 010 so precautions need be taken. Elaborating the
feedback will usually do it.
--
"If you want to post a followup via groups.google.com, don't use
the broken "Reply" link at the bottom of the article. Click on
"show options" at the top of the article, then click on the
"Reply" at the bottom of the article headers." - Keith Thompson |
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Glenn Gundlach
Guest
|
| Posted:
Sat Feb 12, 2005 6:10 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
Well sir, I beg to differ a little. My TV remote transcoder boards are
in transit from Advanced Circuits. It uses a 68HC908JK3 to listen to
the IR receiver. I needed a 38kHz for pulsing the IR transmit LED. With
the 32MHz osc, thats divide by 840 so I have an 'F163 to prescale by 15
to
2.133MHz and then do the rest of the counting and gating in a 22V10
(38095 Hz is close enough). It divides by 56 with a 50/50 duty cycle by
counting from 4 to 60 in the 6 bit counter and then the IRQ to the
controller and the gating with the transmit, also from the controller.
The 22V10 is just dandy for this in spite of being a power hog. I can
live with it. Using MSI counters would have been more tedious to work
out and would have used more packages. Gating changes in a GAL are
easily reprogrammed.
GG |
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Fred Bloggs
Guest
|
| Posted:
Sat Feb 12, 2005 6:11 am Post subject:
Re: Clock Divider in a 22V10 |
|
|
| Quote: |
I have a 6.144Mhz crystal and I am trying to
generate the 9600*16 ~ 154k clock needed by the
8251 UART and the ~ 1Mhz system clock.
I dont want to use the 74ls* series ripple
counters and I have a bunch of 22v10 PAL chips
lying around.
I have been thinking about how best to do this,
using what I have.
Basically I need to divide the 6.144Mhz by 40.
First by 5 to realize the system clock, then by
8 to realize the UART baud clock.
With the 22v10 I could set aside two 3 bit
"registered" outputs for a GLITCH FREE
synchronous counter ... But I would need the
output of one to drive the other ... and I
dont see how I can do this when they all
share a common CLK input.
By the way I also have a bunch of 74ls112 dual
J/K flip flops lying around (about 25). I
thought I might use that along with the 22v10'
to realize my clock divider.
|
The 22V10 is not appropriate for a simple task like this one- the job
can be done for about $0.70 (qty 1 ea.) with more readily available and
better performing MSI logic in a 14-pin IC like shown below. The
74HCT393 is a dual 4-bit ripple counter arranged so that 1CTR cycles
through states 0->4. The transition into state 5 is transient in that
the NAND decodes Q0,Q2 hazard free to apply a negative transition to
/2CLK which advances from state 0->1 so that 2Q0 clears 1CTR- then the
CLK clears 2CTR during its HIGH state removing the 1CLR through 2Q0 well
in advance of the next CLK H->L transition on /1CLK for a repeat of the
sequence. The 1Q1 is a solid 40/60 duty CLK/5 output. Then you can apply
the CLK/5 to *any* 4-bit binary counter allowed to free run to obtain
/2, /4, /8, /16 from the respective Q0, Q1, Q2, Q3 outputs- and at
perfect 50/50 duty. It is important you use the HCT393 and HCT00 to meet
the various requirements of things like hazard free NAND state decode,
minimum CLK pulse width, reset recovery and a few other more or less
subtle timing considerations that make asynchronous reliable. If you
don't have any spare NANDs then use the other three gates to square up
that CLK input and buffer CLK/5 output.
View in a fixed-width font such as Courier.
,----------------------------------+
| 74HCT393 1/4 |
CLK | ----------- 74HCT00 |
| |____ | __ |
6.144MHz>-+---|-----|1CLK 1Q0|---------| \ |
| | | | | o--'
| | ,--|1CLR 1Q1|--. ,--|__/
| | | | | | |
| | | | 1Q2|------'
| | | | | | CLK
| | | | 1Q3| '--------> --- duty:
| | | | | 5 40/60
| | | | |
| | | | |
| | | | |
| | | |____ |
| '-----|2CLK 2Q0|----.
| | | | |
'---------|2CLR 2Q1| |
| | | |
| | 2Q2| |
| | | |
| | 2Q3| |
| ----------- |
| |
'-------------------' |
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