| Author |
Message |
keith
Guest
|
 Posted:
Tue Sep 27, 2005 7:36 am Post subject:
Re: Divide by N chip |
|
|
On Mon, 26 Sep 2005 00:21:14 -0400, wrote:
| Quote: | Thanks Keith,
I threw together a little bit of VHDL this afternoon, but made some |
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through
and *old* copy Synplify to get an idea of the timing. With even the old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but
I got no usefull speed information (I'm not familliar with the CPLD tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me
know. It really is simple (20 lines or so). I also have the equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post them.
I didn't add your markers, but they're easy to drop in.
--
Keith
|
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petrus bitbyter
Guest
|
| Posted:
Tue Sep 27, 2005 8:35 am Post subject:
Re: Divide by N chip |
|
|
"keith" <krw@att.bizzzz> schreef in bericht
news:pan.2005.09.27.02.36.10.893841@att.bizzzz...
| Quote: | On Mon, 26 Sep 2005 00:21:14 -0400, wrote:
Thanks Keith,
I threw together a little bit of VHDL this afternoon, but made some
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through
and *old* copy Synplify to get an idea of the timing. With even the old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but
I got no usefull speed information (I'm not familliar with the CPLD tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me
know. It really is simple (20 lines or so). I also have the equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post them.
I didn't add your markers, but they're easy to drop in.
--
Keith
|
Keith,
Twenty lines or so can be placed in the group as well. I'm also interested
in this kind of stuff and I guess I'm not the only one.
petrus bitbyter |
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TRABEM
Guest
|
| Posted:
Tue Sep 27, 2005 8:35 am Post subject:
Re: Divide by N chip |
|
|
| Quote: | The 4059 (CD4059, HEF4059) is still available at some places, for
about USD 3.00. To make it run at 15MHz, it requires a higher supply
voltage of 10V to 15V, though.
|
Thanks Martin,
I found a 4059 for about $3. But, the 74HC4059 is much faster
(although still not quite fast enough) and costs $1.60.
It's almost fast enough, need it to operate at 30 Mhz, but it's rated
only for 28 Mhz with a 5 volt supply. Unfortunately, I can't change
the supply voltage and 30 Mhz is bare minimum for my project.
I looked for an 74HCT4059 and a 74AC4059, both of which would be fast
enough, but no one makes them (that I could find). Phillips used to
make the 74HCT4059, but they have sold out to TI, who doesn't make
them now.
Regards,
T
|
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Keith Williams
Guest
|
| Posted:
Tue Sep 27, 2005 4:35 pm Post subject:
Re: Divide by N chip |
|
|
In article <4338f761$0$782$3a628fcd@reader20.nntp.hccnet.nl>,
pieterkraltlaatditweg@enditookhccnet.nl says...
| Quote: |
"keith" <krw@att.bizzzz> schreef in bericht
news:pan.2005.09.27.02.36.10.893841@att.bizzzz...
I threw together a little bit of VHDL this afternoon, but made some
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through
and *old* copy Synplify to get an idea of the timing. With even the old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but
I got no usefull speed information (I'm not familliar with the CPLD tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me
know. It really is simple (20 lines or so). I also have the equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post them.
I didn't add your markers, but they're easy to drop in.
--
Keith
Keith,
Twenty lines or so can be placed in the group as well. I'm also interested
in this kind of stuff and I guess I'm not the only one.
|
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the
VHDL later today (I'd like a chance to simulate and format it for the
narrow screen). Some of the other files are graphics (print to
PDFs). Those are interesting too and I'm not sure where to put 'em.
--
Keith |
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|
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petrus bitbyter
Guest
|
| Posted:
Tue Sep 27, 2005 4:35 pm Post subject:
Re: Divide by N chip |
|
|
"Keith Williams" <krw@att.bizzzz> schreef in bericht
news:MPG.1da314807d5a7bd2989bde@news.individual.net...
| Quote: | In article <4338f761$0$782$3a628fcd@reader20.nntp.hccnet.nl>,
pieterkraltlaatditweg@enditookhccnet.nl says...
"keith" <krw@att.bizzzz> schreef in bericht
news:pan.2005.09.27.02.36.10.893841@att.bizzzz...
I threw together a little bit of VHDL this afternoon, but made some
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it
through
and *old* copy Synplify to get an idea of the timing. With even the
old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left,
but
I got no usefull speed information (I'm not familliar with the CPLD
tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let
me
know. It really is simple (20 lines or so). I also have the
equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post
them.
I didn't add your markers, but they're easy to drop in.
--
Keith
Keith,
Twenty lines or so can be placed in the group as well. I'm also
interested
in this kind of stuff and I guess I'm not the only one.
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the
VHDL later today (I'd like a chance to simulate and format it for the
narrow screen). Some of the other files are graphics (print to
PDFs). Those are interesting too and I'm not sure where to put 'em.
--
Keith
|
Keith,
Can you place it in alt.binaries.schematics.electronics? Otherwise I can
place it somewhere for some time. You can reach me by e-mail when you leave
out the obvious in my address. That's to say obvious in Dutch.
Laatditwegenditook translates Leavethisoutandthistoo.
petrus bitbyter |
|
| Back to top |
|
|
Guest
|
| Posted:
Wed Sep 28, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
Keith Williams skrev:
| Quote: | In article <4338f761$0$782$3a628fcd@reader20.nntp.hccnet.nl>,
pieterkraltlaatditweg@enditookhccnet.nl says...
"keith" <krw@att.bizzzz> schreef in bericht
news:pan.2005.09.27.02.36.10.893841@att.bizzzz...
I threw together a little bit of VHDL this afternoon, but made some
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through
and *old* copy Synplify to get an idea of the timing. With even the old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but
I got no usefull speed information (I'm not familliar with the CPLD tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me
know. It really is simple (20 lines or so). I also have the equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post them.
I didn't add your markers, but they're easy to drop in.
--
Keith
Keith,
Twenty lines or so can be placed in the group as well. I'm also interested
in this kind of stuff and I guess I'm not the only one.
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the
VHDL later today (I'd like a chance to simulate and format it for the
narrow screen). Some of the other files are graphics (print to
PDFs). Those are interesting too and I'm not sure where to put 'em.
--
Keith
|
how about this in verilog:
module divider(clk,divider,clkout);
input clk;
input [7:0] divider;
output clkout;
reg clkout;
reg [7:0] count;
always@(posedge clk)
begin
if(count == 8'd0)
begin
clkout <= ~clkout;
count <= divider;
end
else
begin
count <= count - 8'd1;
end
end
endmodule
going through Xilinx ISE5.1 targeting a xcr3032xl cpld it claims 200MHz
limited by the minimum clk pulse width spec for the part.
-Lasse |
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|
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Guest
|
| Posted:
Wed Sep 28, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
keith skrev:
| Quote: | On Sun, 25 Sep 2005 14:40:38 -0400, wrote:
snip
Do the programming tools use a graphic interface to assemble gates, or
does the user need to know programming?
THere are schematic capture tools, as well as "programming" languages
(Verilog, VHDL, etc.). Personally, I'd rather use VHDL for such a
project. It's easy to pick up for a small application like this. You
could even do structural VHDL and instantiate the registers and logic
directly. IMO, this is a perfect sort of application to get one's "feet
wet".
|
yep, stay away from schematics, though I'd pick verilog its simpler and
much
less to type, but that a whole different discussion.
| Quote: |
Hardware needed for burning the chip and the software for designing it
costs how much?
Dunno. I haven't looked lately. Check the Xilinx site. The programming
cable isn't all that expensive. Software for all but the largest devices
is free. The third party software has more function but does get
quite pricey (I had >$80K in Synplicity software on my laptop at one point).
|
yep go look for "webpack", and the programming cable is basically a
buffer
on the parallelport you could even build your own, I think there's a
schematic
on the xilinx site.
-Lasse |
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|
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Guest
|
| Posted:
Wed Sep 28, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
clicliclic@freenet.de wrote:
| Quote: |
It's worth a try, I think, unless you also want to learn about
programmable
logic. Try to make sure you get a HEF74HC4059.
|
That should have been: "Try to make sure you get a Philips 74HC4059."
Martin. |
|
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|
|
Guest
|
| Posted:
Wed Sep 28, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
TRABEM wrote:
| Quote: |
I found a 4059 for about $3. But, the 74HC4059 is much faster
(although still not quite fast enough) and costs $1.60.
It's almost fast enough, need it to operate at 30 Mhz, but it's rated
only for 28 Mhz with a 5 volt supply. Unfortunately, I can't change
the supply voltage and 30 Mhz is bare minimum for my project.
I looked for an 74HCT4059 and a 74AC4059, both of which would be fast
enough, but no one makes them (that I could find). Phillips used to
make the 74HCT4059, but they have sold out to TI, who doesn't make
them now.
Regards,
T
|
According to the Philips datasheet,
<http://www.semiconductors.philips.com/acrobat_download/datasheets/74HC_HCT4059_CNV_2.pdf>
at room temperature both the HC4059 and HCT4059 typically reach 36MHz
for
VCC=4.5V (!).
It's worth a try, I think, unless you also want to learn about
programmable
logic. Try to make sure you get a HEF74HC4059.
I'm not sure there ever was an AC4059.
Martin. |
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| Back to top |
|
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Keith Williams
Guest
|
| Posted:
Wed Sep 28, 2005 4:35 pm Post subject:
Re: Divide by N chip |
|
|
In article <1127853861.317133.45810@g43g2000cwa.googlegroups.com>,
langwadt@ieee.org says...
| Quote: |
Keith Williams skrev:
In article <4338f761$0$782$3a628fcd@reader20.nntp.hccnet.nl>,
pieterkraltlaatditweg@enditookhccnet.nl says...
"keith" <krw@att.bizzzz> schreef in bericht
news:pan.2005.09.27.02.36.10.893841@att.bizzzz...
I threw together a little bit of VHDL this afternoon, but made some
assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through
and *old* copy Synplify to get an idea of the timing. With even the old
SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but
I got no usefull speed information (I'm not familliar with the CPLD tools
and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me
know. It really is simple (20 lines or so). I also have the equivalent
schematics ("HDL Analyst"), but I'm not quite sure how best to post them.
I didn't add your markers, but they're easy to drop in.
--
Keith
Keith,
Twenty lines or so can be placed in the group as well. I'm also interested
in this kind of stuff and I guess I'm not the only one.
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the
VHDL later today (I'd like a chance to simulate and format it for the
narrow screen). Some of the other files are graphics (print to
PDFs). Those are interesting too and I'm not sure where to put 'em.
--
Keith
how about this in verilog:
module divider(clk,divider,clkout);
input clk;
input [7:0] divider;
output clkout;
reg clkout;
reg [7:0] count;
always@(posedge clk)
begin
if(count == 8'd0)
begin
clkout <= ~clkout;
count <= divider;
end
else
begin
count <= count - 8'd1;
end
end
endmodule
|
Looks an awfully lot like the VHDL I threw together ;-):
library ieee; -- needed for the below libraries
use ieee.std_logic_1164.all; -- standard logic functions/signals
use ieee.std_logic_unsigned.all ; -- arithmetic package (the subtract 1)
entity ClockDivider is -- define logic block
port ( -- I/O name list
Clock: in std_logic; -- 30MHz reference clock
Reset: in std_logic; -- System asynchronous reset
DivideBy: in std_logic_vector(8 downto 0); -- Devide by number
ClockOut: out std_logic -- Devided clock output
);
end ClockDivider; -- end of entity
architecture Divider of ClockDivider is -- design definition
-- define internal signals
signal count: std_logic_vector(8 downto 0); -- divide by n counter
begin -- start design
DivideByN: PROCESS (Clock, Reset) -- Divide by N circuit
BEGIN -- begin sequential logic
IF Reset = '1' -- If asynchronous reset
THEN -- THEN
Count <= "000000000"; -- Clear counter
ClockOut <= '0'; -- Clear output T-FF
ELSIF rising_edge(CLock) -- ELSE IF rising clock
THEN -- THEN
IF Count = "000000000" -- IF count is zero
THEN -- THEN
Count <= DivideBy; -- SET divide by
ClockOut <= NOT ClockOut; -- Flip output
ELSE -- ELSE
Count <= Count -1; -- Decrement count
END IF;
END IF;
END PROCESS;
end Divider;
| Quote: |
going through Xilinx ISE5.1 targeting a xcr3032xl cpld it claims 200MHz
limited by the minimum clk pulse width spec for the part.
|
Synplify says it'll do 200MHz on a VirtexE. It doesn't have timing information
for CoolRunners or Altera devices. BTW, I don't believe what the synthesizer
says. They typically don't weight wiring high enough. Wiring is a larger
portion of the total delay for each successive technology.
--
Keith
--
Keith |
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Chris Jones
Guest
|
| Posted:
Sat Oct 01, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
TRABEM <> wrote:
| Quote: | Ok, what are your jitter requirements? Duty cycle?
Not sure about a number. But, the DDS chips have spurs and the PLL's
have phase noise. The quadrature receiver is capable of very high
performance and it's much easier to build-hardly any tuned circuits to
deal with and is much cheaper to build as well.
So, quartz is still be best when one needs a high quality local
oscillator. I want to use a quartz crystal with a divide by N to get
the quartz performance and some minimal frequency agility (at LF
receive frequencies) by varying the divide by N value.
It was my hope that starting with a clean quartz oscillator, then
dividing it down would result in a high quality LO that would be
similar in performance to the crystal alone and give me some minimal
frequency agility.
The receiver I'm looking at is the softrock-40 unit shown
http://www.amqrp.org/kits/softrock40/index.html
I plan to convert the receiver to 160 to 190 Khz by dividing down a 30
Mhz crystal oscillator, which makes the LO easy to build and gives
good performance in a small package. It does not allow the frequency
agility of a DDS or a PLL, but I don't need the frequency agility
anyway.
The duty cycle is of no concern, I just need an output that goes high
long enough for the input logic to recognize the transition.
Regards,
T
|
I guess you know that spurs and phase noise go down by almost 6dB every time
you divide a signal by two in frequency, so you could get pretty good phase
noise if you took one of those Analog Devices ADF4360-X PLL chips with the
integrated VCO, and divide down the output to 160-190kHz. If you start
with a 2GHz-ish frequency and end up with 200kHz-ish, then the phase noise
ought to go down to 80dB below whatever the PLL puts out, which should be
pretty good and is probably limited by thermal noise etc. You do need a
fixed divider which runs at a few GHz to divide down this VCO, and you
could use something like an ADF4112 as the divider if you set it to mux the
divider output to a pin. You will however need a PIC or something to
program the two chips. You'll probably need a proper PCB to get decent
performance, though I have had some success soldering 0402 components
directly to the back of a LFCSP and wiring the RF up with 1mm semi-rigid
coax - under a good microscope! I have not tried this with the parts I
mentioned above though.
Hope this helps
Chris |
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Jon Jacob
Guest
|
| Posted:
Sat Oct 01, 2005 4:35 pm Post subject:
Re: Divide by N chip |
|
|
| Quote: |
Twenty lines or so can be placed in the group as well. I'm also
interested
in this kind of stuff and I guess I'm not the only one.
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the
VHDL later today (I'd like a chance to simulate and format it for the
narrow screen). Some of the other files are graphics (print to
PDFs). Those are interesting too and I'm not sure where to put 'em.
--
Keith
Keith,
Can you place it in alt.binaries.schematics.electronics? Otherwise I can
place it somewhere for some time. You can reach me by e-mail when you leave
out the obvious in my address. That's to say obvious in Dutch.
Laatditwegenditook translates Leavethisoutandthistoo.
petrus bitbyter
Were these files posted to the a.b.s.e? There was nothing in |
the time frame that looked applicable. Thanks. -jon |
|
| Back to top |
|
|
Joop
Guest
|
| Posted:
Sun Oct 02, 2005 12:35 am Post subject:
Re: Divide by N chip |
|
|
TRABEM <> wrote:
<one post>
My entire project involves a programmable binary divider, with
programming being done by outboard switches to gate the desired
combination of outputs back to the reset on the counter so that free
running divide by N from 2 to 255 is all that's needed, with a 20 Mhz
input to divide by N.
<another post>
| Quote: | It's almost fast enough, need it to operate at 30 Mhz, but it's rated
only for 28 Mhz with a 5 volt supply. Unfortunately, I can't change
the supply voltage and 30 Mhz is bare minimum for my project.
|
Do you really need 30MHz? Or is 20MHz also good as you mentioned in an
earlier post.
Because if 20MHz is ok, then you could do what I recently did with a
PIC micro. The PWM output can be set to FOSC/N with N=[4..4096].
I used it to generate a clock/6 signal I needed in a PLL circuit. Just
a few lines of code required.
Mine was an 8 pins 12F683 @ 1 Euro. But if you need more inputs for
your switches, an 16F88 or similar would do I guess.
If you don't really need fixed frequencies the 12F683 could read a pot
with its analog input and vary N this way. Just an idea.
Joop |
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TRABEM
Guest
|
| Posted:
Sun Oct 02, 2005 11:02 pm Post subject:
Re: Divide by N chip |
|
|
Thanks Martin,
There is good news. By tightening up some other parts specs, I was
able to get the minimum usable clock frequency down to 12.8 Mhz. This
allows a TCXO similar to those used in cell phones to be used...which
makes it even easier to implement with high stability.
By the way, Phillips has sold their digital chip division to TI and
the Phillips digital cmos parts are slowly disappearing from the
market as the remaining stock is sold by distributors.
I did a spot check however, and the HCT and the HC parts are made by
TI now, which is good news. In fact, TI is distributing the Phillips
PDF's through their website....so it appears the Phillips parts will
live on, at least for awhile longer.
I think I've found a source for inexpensive 12.8 Mhz TCXO's, so it
looks like I'll use them with a couple of AND gates to get my divided
down LF and VLF frequencies.
Regards,
T
| Quote: |
It's worth a try, I think, unless you also want to learn about
programmable
logic. Try to make sure you get a HEF74HC4059.
That should have been: "Try to make sure you get a Philips 74HC4059."
Martin. |
|
|
| Back to top |
|
|
SioL
Guest
|
| Posted:
Sun Oct 02, 2005 11:35 pm Post subject:
Re: Divide by N chip |
|
|
<TRABEM> wrote in message news:t480k1p1l7dnvjh4ainl4767rtl93vj1s4@4ax.com...
| Quote: | I think I've found a source for inexpensive 12.8 Mhz TCXO's, so it
looks like I'll use them with a couple of AND gates to get my divided
down LF and VLF frequencies.
|
These TCXO's are interesting. Where did you find them?
SioL |
|
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