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valentin tihomirov
Guest
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 Posted:
Thu Feb 10, 2005 4:51 pm Post subject:
Synchronous logic: Tpd |
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Hello,
A noob needs some clarification on the crusal design basics. The
http://www.fairchildsemi.com/ds/74/74VHC595.pdf shift register allow for
cascading Q' pin output pin to SER data input. However, I have discovered an
interesting fact - the new value at the output may apperar earlier
(propagation delay = 1ns) than the hold time of SER allows (2ns). Isn't this
logic familiy designed for synchronous operation?
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Fred Bloggs
Guest
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| Posted:
Fri Feb 11, 2005 6:17 pm Post subject:
Re: Synchronous logic: Tpd |
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valentin tihomirov wrote:
| Quote: | Hello,
A noob needs some clarification on the crusal design basics. The
http://www.fairchildsemi.com/ds/74/74VHC595.pdf shift register allow for
cascading Q' pin output pin to SER data input. However, I have discovered an
interesting fact - the new value at the output may apperar earlier
(propagation delay = 1ns) than the hold time of SER allows (2ns). Isn't this
logic familiy designed for synchronous operation?
|
That "1ns" column for a "minimum" Tpd over temperature is a bogus
number. Any operating condition that reduces the Tpd will also reduce
the minimum Th. The inportant thing is that Tpd will remain ~5x Th. You
will encounter no problems. |
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valentin tihomirov
Guest
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| Posted:
Sat Feb 12, 2005 2:16 am Post subject:
Re: Synchronous logic: Tpd |
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| Quote: | That "1ns" column for a "minimum" Tpd over temperature is a bogus
number. Any operating condition that reduces the Tpd will also reduce
the minimum Th. The inportant thing is that Tpd will remain ~5x Th. You
will encounter no problems.
|
But the 2ns is the minimum Th as well, so the operating condition reducing
Tpd => 1ns will reduce Th => 2ns limit. This makes the safe operation (Tpd
~5xTh) impossible.
Additional thing which needs clarification is the upper limit of Th. Why do
they specify the lowest threshold if the parameter is longer in reality? Do
they want me to retain the input signal constant during the minimal time or
it must last some longer? IMO, it is the maximal Th, which have to be
satisfied (and specified) in order for the device to switch propertly.
Thanks.
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Fred Bloggs
Guest
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| Posted:
Sat Feb 12, 2005 6:11 am Post subject:
Re: Synchronous logic: Tpd |
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valentin tihomirov wrote:
| Quote: | That "1ns" column for a "minimum" Tpd over temperature is a bogus
number. Any operating condition that reduces the Tpd will also reduce
the minimum Th. The inportant thing is that Tpd will remain ~5x Th. You
will encounter no problems.
But the 2ns is the minimum Th as well, so the operating condition reducing
Tpd => 1ns will reduce Th => 2ns limit. This makes the safe operation (Tpd
~5xTh) impossible.
|
That 2ns in the datasheet is the single value of Th guaranteed to work
over -40<Ta<+85 oC, it does not mean that a lesser Th will not work
under fixed operating conditions. The logic was designed so that Tpd>Th
for every instance of operating conditions.
| Quote: |
Additional thing which needs clarification is the upper limit of Th. Why do
they specify the lowest threshold if the parameter is longer in reality? Do
they want me to retain the input signal constant during the minimal time or
it must last some longer? IMO, it is the maximal Th, which have to be
satisfied (and specified) in order for the device to switch propertly.
|
You should translate "minimum" to mean: can be removed no sooner than Th
after SCLK transition. SER must remain valid for Th nsecs after the SCLK
edge. Any additional time you hold SER is wasted, the clocking action is
finished, and the SER input no longer has any effect. A maximal Th would
be something like Tclk-Tsetup and has nothing to do with hold time. |
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Rich Grise
Guest
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| Posted:
Sun Feb 13, 2005 2:26 pm Post subject:
Re: Synchronous logic: Tpd |
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On Thu, 10 Feb 2005 12:51:58 +0200, valentin tihomirov wrote:
| Quote: | Hello,
A noob needs some clarification on the crusal design basics. The
http://www.fairchildsemi.com/ds/74/74VHC595.pdf shift register allow for
cascading Q' pin output pin to SER data input. However, I have discovered an
interesting fact - the new value at the output may apperar earlier
(propagation delay = 1ns) than the hold time of SER allows (2ns). Isn't this
logic familiy designed for synchronous operation?
|
Yes, the family is designed for synchronous operation, which means that
meeting the setup times by a 2X margin makes them robust and reliable.
In other words, what is the state of these ins and outs at the clock
transition?
Cheers!
Rich |
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